The present invention relates in general to the field of mass storage devices, and more particularly to a system and method for enhancing write-to-read switching times in a preamplifier circuit.
Hard disk drives such as the exemplary drive 10 illustrated in FIG. 1 include a stack of magnetically coated platters 12 that are used for storing information. The magnetically coated platters 12 are mounted together in a stacked position through a spindle 14 which may be referred to as a platter stack. The platter stack is typically rotated by a motor that is referred to as a spindle motor or a servo motor (not shown). A space is provided between each platter to allow an arm 18 having a read/write head or slider 20 associated therewith to be positioned on each side of each platter 12 so that information may be stored and retrieved. Information is stored on each side of each platter 12 and is generally organized into sectors, tracks, zones, and cylinders.
Each of the read/write heads or sliders 20 are mounted to one end of the dedicated suspension arm 18 so that each of the read/write heads may be positioned as desired. The opposite end of each of the suspension arms 18 are coupled together at a voice coil motor 16 (VCM) to form one unit or assembly (often referred to as a head stack assembly) that is positionable by the voice coil motor. Each of the suspension arms 18 are provided in a fixed position relative to each other. The voice coil motor 16 positions all the suspension arms 18 so that the active read/write head 20 is properly positioned for reading or writing information. The read/write heads 20 may move from at least an inner diameter to an outer diameter of each platter 12 where data is stored. This distance may be referred to as a data stroke.
Hard disk drives also include a variety of electronic circuitry for processing data and for controlling its overall operation. This electronic circuitry may include a preamplifier, a read channel, a write channel, a servo controller, a motor control circuit, a read-only memory (ROM), a random-access memory (RAM), and a variety of disk control circuitry (not shown) to control the operation of the hard disk drive and to properly interface the hard disk drive to a system bus. The preamplifier may contain a read preamplifier and a write preamplifier that is also referred to as a write driver. The preamplifier may be implemented in a single integrated circuit or in separate integrated circuits such as a read preamplifier and a write preamplifier or write driver. The disk control circuitry generally includes a separate microprocessor for executing instructions stored in memory to control the operation and interface of the hard disk drive.
Hard disk drives perform write, read, and servo operations when storing and retrieving data. Generally, a write operation includes receiving data from a system bus and storing the data in the RAM. The microprocessor schedules a series of events to allow the information to be transferred from the RAM to the platters 12 through the write channel. Before the information is transferred, the read/write heads 20 are positioned on the appropriate track and the appropriate sector of the track is located. The data from the RAM is then communicated to the write channel as a digital write signal. The write channel processes the digital write signal and generates an analog write signal. In doing this, the write channel may encode the data so that the data can be more reliably retrieved later. The digital write signal may then be provided to an appropriate read/write head 20 after first being conditioned by the preamplifier. Writing data to the recording medium or platter 12 is typically performed by applying a current to a coil of the head 20 so that a magnetic field is induced in an adjacent magnetically permeable core, with the core transmitting a magnetic signal across a spacing of the disk to magnetize a small pattern or digital bit of the media associated with the disk.
Circuitry associated with a read operation is illustrated in FIG. 2, and designated at reference numeral 30. In a read operation, the appropriate sector to be read is located and data that has been previously written to the platters 12 is detected. The appropriate read/write head 20 (illustrated as a magneto-resistive load 20a in FIG. 2) senses the changes in the magnetic flux and generates a corresponding analog read signal. The analog read signal is provided back to the electronic circuitry where a preamplifier circuit 32 amplifies the analog read signal. The amplified analog read signal is then provided to a read channel circuit 34 where the read channel conditions the signal and detects xe2x80x9czerosxe2x80x9d and xe2x80x9conesxe2x80x9d from the signal to generate a digital read signal. The read channel may condition the signal by amplifying the signal to an appropriate level using, for example, automatic gain control (AGC) techniques. The read channel may then filter the signal to eliminate unwanted high frequency noise, equalize the channel, perform the data recovery from the signal, and format the digital read signal. The digital read signal is then transferred from the read channel and is stored in the RAM (not shown). The microprocessor may then communicate to the host that data is ready to be transferred.
The read channel circuit 34 may be implemented using any of a variety of known or available read channels. For example, the read channel 34 may be implemented as a peak detection type read channel or as a more advanced type of read channel utilizing discrete time signal processing. The peak detection type read channel involves level detecting the amplified analog read signal and determining if the waveform level is above a threshold level during a sampling window. The discrete time signal processing type read channel synchronously samples the amplified analog read signal using a data recovery clock. The sample is then processed through a series of mathematical manipulations using signal processing theory to generate the digital read signal. There are several types of discrete time signal processing read channels such as a partial response, maximum likelihood (PRML) channel; an extended PRML channel; an enhanced, extended PRML channel; a fixed delay tree search channel; and a decision feedback equalization channel.
As the disk platters 12 are rotating, the read/write heads 20 must align or remain on a particular track in order to accurately read the data thereon. This is accomplished by a servo operation through the use of a servo controller provided in a servo control loop. Referring to FIG. 3 which represents a plan view of an exemplary platter 12, in a servo operation a servo wedge 40 is read from a track 42 that generally includes track identification information and track misregistration information 44. The track misregistration information may also be referred to as position error information. The position error information 44 may be provided as servo bursts and may be used during both read and write operations to ensure that the read/write heads are properly aligned on a track. As a result of receiving the position error information, the servo controller generates a corresponding control signal to position the read/write heads 20 via the voice coil motor. The track identification information 44 from the servo wedge 40 is also used during read and write operations so that a track 42 may be properly identified.
Hard disk drive designers strive to provide higher capacity drives that operate at a high signal-to-noise ratio and a low bit error rate. To achieve higher capacities, the density of the data stored on each side of each platter must be increased. This places significant burdens on the hard disk drive electronic circuitry. For example, as the density increases, the magnetic transitions that are used to store data on the platters must be physically located more closely together. This often results in intersymbol interference when performing a read operation. As a result, the hard disk drive electronic circuitry must provide more sophisticated processing circuitry that operates at higher frequencies to accurately process the intersymbol interference and the higher frequency read signal. In some cases, the spindle motor speed is increased which further increases the frequency of the read signal and the write signal. Furthermore, the increase in density requires that the servo control system be provided with a higher bandwidth to increase the read/write head positioning resolution.
As discussed above, to account for the increased data storage density, the spindle motor speed is being increased from a platter rotational speed of about 5400 RPMs to about 7200 RPMs or greater. To account for the increased speed, the write-to-read transition timing for a head 20 becomes important. For example, when performing a write operation, the head 20 is traversing a track 42 on the platter 12 as the platter spins there beneath. As illustrated in FIG. 3, when a servo region or wedge 40 is encountered, the head 20 must quickly transition from a write state to a read state in order to read the servo information stored therein and then quickly transition back to a write state in order to continue writing the data to the platter 12. If the write-to-read transition timing is slow, then the servo wedge 40 must be larger since the platter is rotating at a generally constant speed. Since many servo wedges 40 exist on the platter 12 (e.g., about 60) an optimized write-to-read transition timing allows for the wedges 40 to be minimized, thereby increasing data storage density thereon.
There is a need in the art to provide a preamplifier circuit which exhibits reduced write-to-read switching times.
The present invention relates to a system and method for reducing a write-to-read switching time in a hard disk drive preamplifier circuit.
According to the present invention, the write-to-read switching time is reduced from conventional preamplifier circuits by incorporating a concurrent application of DC bias voltages to all stages of the preamplifier circuit while instituting a staggered squelch deactivation mechanism to prevent saturation of the preamplifier circuit. By applying the DC bias voltages to all stages of the preamplifier circuit substantially concurrently, a settling time associated with all the amplifier stages is reduced, thereby allowing the preamplifier circuit to begin reading data at an earlier time when switching from a write state to a read state. In addition, the staggered squelch deactivation mechanism allows for the concurrent application of DC bias voltages by preventing glitches that may be generated by the DC bias voltages from saturating the amplifier circuit.
The present invention also may include a pole shifting component in the preamplifier circuit that is operable to prevent low frequency glitches that may occur due to the staggered squelch deactivation mechanism from saturating the preamplifier circuit. The pole shifting component is selectively employable or programmable such that upon activation, a pole is shifted for a predetermined period of time, at which point a cutoff frequency associated with a high pass filter is increased to ensure rejection of any such glitches through the preamplifier circuit. After the predetermined time, the pole is shifted back to its original position, thereby reducing the cutoff frequency of the high pass filter to permit reading of data at lower frequencies in an expeditious manner.
According to one aspect of the present invention, a preamplifier circuit comprises a plurality of amplifier stages which are operable to consecutively amplify a signal detected by a head of a hard disk drive. The preamplifier circuit further comprises a power delivery circuit which is operably coupled to the amplifier stages and operable to provide power to each of the amplifier stages in a substantially concurrent manner, thereby reducing a settling time associated therewith. In addition, a control circuit is operably coupled to the amplifier stages and is operable to activate the amplifier stages by deactivating a squelch mechanism associated therewith in a staggered manner, thereby eliminating or otherwise mitigating glitches associated with the substantially concurrent application of power to the amplifier stages from saturating the preamplifier circuit.
According to another aspect of the present invention, the preamplifier circuit comprises a pole shifting circuit operably coupled to one of the amplifier stages which is operable to interface with such amplifier stage to form a programmable high pass filter circuit. The high pass filter may be programmable to the extent that when a read state is detected, for example, the cutoff frequency associated therewith is increased to reject low frequency noise which may be generated by the concurrent DC bias application and/or the staggered squelch deactivation and thus prevent saturation of the preamplifier circuit. After a predetermined period of time, the cutoff frequency is decreased by shifting a pole associated therewith to about its original position to allow for passing of data therethrough which may exist at lower signal frequencies.
According to still another aspect of the present invention, a preamplifier circuit comprises a plurality of differential amplifier stages coupled together in series. The preamplifier circuit comprises a DC bias delivery circuit which is operable to delivery positive and negative DC bias voltages to each of the amplifier stages at about the same time when a read mode is detected. Application of such DC bias voltages to each of the amplifier stages at about the same time reduces an aggregate settling time for all of the amplifier stages and thus permits reading data more quickly than conventional solutions. In addition, the preamplifier circuit comprises a squelch circuit which is operable to short out the differential input or output of multiple amplifier stages in a staggered manner according to a predetermined timing after the read mode is detected. By staggering a deactivation of various squelch conditions for the multiple amplifier stages, glitches associated with the substantially concurrent DC bias voltage application and earlier squelch deactivations are prevented from saturating the preamplifier circuit.
According to yet another aspect of the present invention, a programmable high pass filter circuit operates in conjunction with the above DC bias delivery circuit and the squelch circuit to prevent low frequency noise or glitches associated therewith from adversely impacting a write-to-read switching time. The programmable high pass filter is operable to shift a pole upon a detection of a read mode to increase a cutoff frequency associated therewith. Consequently, any low frequency glitches or excursions that may be generated by the squelch circuit is rejected in the preamplifier circuit during write-to-read switching. After a predetermined period of time, the cutoff frequency is reduced by shifting back the pole to about its original position to allow for low frequency data which is read by the head to pass therethrough.
According to another aspect of the present invention, a method of reducing a write-to-read switching time in a hard disk drive preamplifier circuit is disclosed. The method comprises detecting an initiation of a read mode and coupling DC bias voltages to a plurality of amplifier stages in the preamplifier circuit at about the same time. Consequently, an aggregate settling time associated with the powering up of the amplifier stages is reduced. In addition, the method comprises selectively activating the amplifier stages in a predetermined order by deactivating one or more squelch conditions associated therewith in a staggered fashion upon detection of the detected read state. Such selective activation prevents glitches associated with the application of the DC bias voltages from saturating the preamplifier circuit.
According to still another aspect of the present invention, the method of reducing the write-to-read switching time further comprises increasing a cutoff frequency of a high pass filter associated with the amplifier stages upon detecting the read state to thereby reject low frequency glitches or noise caused by the DC bias voltages or the selective activation of the amplifier stages in a predetermined order. After a predetermined period of time, the cutoff frequency is reduced back to an original value to thereby allow low frequency data signals to pass therethrough.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.